Verilog Digital System Design : Register Transfer Level Synthesis, Testbench, and Verification

By:

Zainalabedin Navabi

Material type: Text

TextLanguage: ENG Publication details: New Delhi Tata McGraw Hill Publishing Co. Limited 2008Edition: 2nd EdDescription: 383pISBN:

0-07-025221-1

DDC classification:

621.381958 NAV

Tags from this library: No tags from this library for this title. Log in to add tags.

Average rating: 0.0 (0 votes)

Holdings
Item type	Current library	Call number	Copy number	Status	Barcode
GENERAL	University of Agricultural Sciences, Dharwad	621.381958/NAV	1	Available	87020
GENERAL	University of Agricultural Sciences, Dharwad	621.381958/NAV	2	Available	87021

Zainalabedin Navabi: Verilog Digital System Design : Register Transfer Level Synthesis, Testbench, and Verification. (2nd Ed) New Delhi. Tata McGraw Hill Publishing Co. Limited, 2008. 0-07-025221-1--(621.381958NAV)

ENGLISH

There are no comments on this title.

to post a comment.

Place hold
Print
Cite
Add to your cart (remove)
Save record
BIBTEX Dublin Core MARCXML MARC (non-Unicode/MARC-8) MARC (Unicode/UTF-8) MARC (Unicode/UTF-8, Standard) MODS (XML) RIS ISBD
More searches

Search for this title in:
Other Libraries (WorldCat) Other Databases (Google Scholar) Online Stores (Bookfinder.com) Open Library (openlibrary.org)