Verilog Digital System Design : Register Transfer Level Synthesis, Testbench, and Verification - Zainalabedin Navabi (New Delhi Tata McGraw Hill Publishing Co. Limited, 2008)
Zainalabedin Navabi: Verilog Digital System Design : Register Transfer Level Synthesis, Testbench, and Verification. (2nd Ed) New Delhi. Tata McGraw Hill Publishing Co. Limited, 2008. 0-07-025221-1--(621.381958NAV)
ENGLISH