TY  - BOOK
AU  - Zainalabedin Navabi
TI  - Verilog Digital System Design : Register Transfer Level Synthesis, Testbench, and Verification
SN  - 0-07-025221-1
U1  - 621.381958 
PY  - 2008///
CY  - New Delhi
PB  - Tata McGraw Hill Publishing Co. Limited
N1  - Zainalabedin Navabi: Verilog Digital System Design : Register Transfer Level Synthesis, Testbench, and Verification.  (2nd Ed)  New Delhi.  Tata McGraw Hill Publishing Co. Limited, 2008. 0-07-025221-1--(621.381958NAV)
ER  -